This invention relates to a device responsive to an input pulse sequence comprising input information bits or pulses for producing an output pulse sequence in synchronism with a sequence of reference clock pulses with stuff or justification bits or pulses interspersed in the output pulse sequence among output information bits or pulses derived from the respective input information pulses. Such a pulse stuff synchronization device is useful in a multiplexer used at a transmitting end of a time division multiplexed digital communication network because the device raises the network flexibility and facilitates the network design.
As described in an article contributed by E. R. Brigham et al. to "The Post Office Electrical Engineers' Journal," Vol. 69 (1976), No. 2, pages 93-102, under the title of "Multiplexing for a Digital Main Network," predetermined number, such as four of plesiochronous lower order pulse sequences are supplied to a multiplexer through input tributaries at a transmitting end of a time division multiplexed digital communication network. Each lower order pulse sequence comprises lower order bits or pulses at a lower bit rate. The multiplexer multiplexes the lower order pulse sequences into a higher order pulse sequence of a higher bit rate. Another multiplexer at the transmitting end may use such higher order pulse sequences as lower order synchronous or plesiochronous pulse sequences therefor in producing another higher order pulse sequence. The multiplexing may be carried out at another transmitting end of the network. The process may be repeated to provide a very high order pulse sequence. At a receiving end of the network, a demultiplexer demultiplexes a higher order pulse sequence supplied thereto into reproductions of the lower order pulse sequences which are multiplexed at a transmitting end into the supplied higher order pulse sequence. The multiplication may be carried out either with information pulses of the respective lower order pulse sequences interleaved in the higher order pulse sequence or with groups of such information pulses interleaved. It will be assumed in the following that bit interleaving is resorted to.
In a multiplexer, a pulse stuff synchronization device is usually used to convert each of the lower order pulse sequences supplied thereto as an input pulse sequence into an output pulse sequence of the type described. The output pulse sequence has consecutive output bit positions specified by the respective reference clock pulses and having a common duration or width called an output bit period. The output bit positions will herein be referred to simply as the time or pulse slots. Such output pulse sequences are multiplexed into the higher order pulse sequence. The reference clock pulse sequence defines an output bit rate of the output pulse sequence. The output bit rate is equal to the higher bit rate divided by the predetermined number. Pulse slots of the respective output pulse sequences, one from each output pulse sequence, are arranged in succession at a plurality of higher order bit positions, respectively.
The higher order pulse sequence is divisible into a succession of frames, each consisting of a prescribed number of higher order bit positions. Each frame thus has a prescribed frame length or period. The demultiplexer must be capable of determining which higher order bit positions are assigned in the respective frames to which lower order pulse sequence . Each frame therefore includes several frame synchronizing or alignment bits or pulses at predetermined ones of the higher order bit positions, respectively.
Each pulse stuff synchronization device comprises an elastic memory having several one-bit memory cells for storing consecutive input information pulses, equal in number to the memory cells at a time. The input information pulses stored in the elastic memory in a cyclic manner from time to time are read out as the respective output information pulses.
The output pulse sequence is also divisible into a succession of frames, each having the prescribed frame period. Each frame thus has a preselected number of pulse slots in succession. The preselected number is equal to the prescribed number divided by the predetermined number. According to a numerical example, the preselected number is two hundred and twelve. In this event, the pulse slots are serially numbered in each frame from No. 1 to No. 212. It is possible to identify the pulses in the respective pulse slots by the use of the serial numbers for the pulse slots. Three pulse slots at the beginning or leading end portion of each frame, namely, the No. 1 through No. 3 pulse slots, are usually used for no output information pulses. This is because the frame alignment pulses and similar service bits or pulses are later placed in these three pulse slots on multiplexing. A predetermined pulse slot in each frae, such as the No. 161 pulse slot, is used as a stuffable or justifiable slot in which either an output information pulse or a stuff pulse is placed. In this sense, the stuffable slot is called a variable slot. Either the output information pulse or the stuff pulse located in the variable slot may be named a variable pulse. At least one predetermined pulse slot in each frame is used as a stuff orjustification control slot. Preferably, three predetermined pulse slots, such as the No. 54, No. 107, and No. 160 pulse slots, are used as first through third stuff control slots for stuff or justification control bits or pulses which are indicative, according to the majority decision, of presence of the output information pulse and of the stuff pulse in the variable slot next following the stuff control slots in question. Other pulse slots are exclusively for the output information pulses. The pulse slots in which the respective output information pulses can be placed, including the variable slot, will herein be called information slots. The pulse slots other than the information slots will herein be named service slots, excluding the variable slots even if a stuff pulse, rather than an output information pulse, is situated therein. According to the numerical example, each frame has two hundred and six information slots.
The input pulse sequence has a succession of input bit positions having a common input bit period and defined by an input clock pulse sequence of the lower bit rate, which may now be called an input bit rate. The input bit positions may include service bit positions similar to the service slots. Other input bit positions are information bit positions for the respective input information pulses. Merely for simplicity of description, it will be presumed in the following that all input bit positions are the information bit positions unless otherwise specified.
The input information pulses are stored in the elastic memory by the use of a plurality of write pulse sequences, equal in number to the memory cells, into which the input clock pulse sequence is distributed. The stored pulses are read out by a plurality of read pulse sequences, again equal in number to the memory cells, into which the reference clock pulse sequence is distributed. It is to be noted here that the stored pulses should not be read out at the service slots. The reference clock pulse sequence should therefore be gapped, prior to distribution, at the reference clock pulses indicative of the service slots. Such a gapped reference clock pulse sequence will, however, be referred to merely as a reference clock pulse sequence in the following because the instant invention has no concern with presence of the service slots in the output pulse sequence.
As described, at least the service pulses are inserted in the output pulse sequence in practice. The output bit rate must therefore be a little higher than the input bit rate. The write pulse sequences should nevertheless have a first phase that always leads a second phase had by the read pulse sequences. In other words, the second phase should always have a phase lag relative to the first phase. This is mandatory for correct read out of the output information pulses. According to the numerical example, the phase lag should correspond to a few input bit periods or output bit periods when an input information pulse is read out of the elastic memory as an output information pulse for the first time in each frame, namely, as the No. 4 output information pulse.
The pulse stuff synchronization device further comprises a phase lag monitor for use in monitoring the phase lag. When the phase lag decreases below a predetermined threshold in a certain frame at an instant herein called a monitor slot of the frame, the phase lag monitor produces a stuff demand pulse for retarding the second phase and for thereby keeping the second phase always behind the first phase. Inasmuch as the phase lag generally decreases in each frae, the monitor slot usually falls in the trailing end portion of each frame, such as from the No. 212 pulse slot back to, for example, the No. 199 pulse slot. The monitor slot is one of the information slots and will later be discussed in detail.
Responsive to the stuff demand pulse, a stuff pulse is subsequently produced. Before production of the stuff pulse, the stuff control pulses in the stuff control slots next following the monitor slot under consideration, namely, in the next succeeding frame, are made to indicate appearance of a stuff pulse in the variable slot that is next subsequent to the stuff control slots in question. If the phase lag is greater than the threshold at the monitor slot, no stuff demand pulse is produced. The stuff control pulses are made to indicate appearance of an output information pulse in the next following variable slot. In order to insert the stuff pulse, the reference clock pulse sequence has to be gapped as will become clear later.
It is known that jitter occurs in the output pulse sequence and consequently in a reproduction of the original input pulse sequence. The jitter adversely affects the quality of the reproduced pulse sequence if not properly suppressed. The jitter includes a waiting time jitter component that results from a waiting time from an instant at which the phase lag actually decreases below the threshold until insertion of a stuff pulse in the next succeeding variable slot. This component may have a low frequency and has been believed to be most detrimental to the quality of the reproduced pulse sequence. It is possible to considerably suppress the waiting time jitter component by a phase lock loop used in the demultiplexer. Furthermore, this component is discussed in various references, the Brigham et al article inclusive.
We have found that another low frequency jitter component remains after suppression of the waiting time jitter component. It is very difficult to suppress the remaining low frequency jitter component by the phase lock loop. As will later be detailed with reference to several figures of the accompanying drawing, we have now analysed that the remaining low frequency jitter component is inevitably produced by a conventional pulse stuff synchronization device.
Briefly describing, the phase lag is monitored in practice by using one each of the write and the read pulse sequences as representatives of the first and the second phases. In other words, the phase lag is sampled at a sampling interval substantially equal to i input bit periods, where i represents the memory capacity of the elastic memory, namely, the number of memory cells. Inasmuch as the effect of sampling is a dominant factor according to our analysis, the remaining low frequency component will be referred to as a sampling jitter component.